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參數(shù)資料
| 型號(hào)： | MPC9892FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 102K |
| 代理商： | MPC9892FA |
3
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9892/D
Rev 0, 12/2002
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
306
Product Preview
Intelligent Dynamic Clock
Switch (IDCS) PLL Clock
Driver
The MPC9892 is a PLL clock driver designed specifically for redundant
clock tree designs. The device receives two differential LVPECL clock
signals from which it generates 5 new differential LVPECL clock outputs.
Two of the output pairs regenerate the input signals frequency and phase
while the other three pairs generate 4x, phase aligned clock outputs. Ex-
ternal PLL feedback is used to also provide zero delay buffer perfor-
mance.
Features:
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3V Operation
32–Lead LQFP Packaging
SiGe technology supports near-zero output skew
Functional Description
The MPC9892 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection
of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary
clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase
disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
Figure 1. Block Diagram
CLK0
CLK1
Ext_FB
Sel_Clk
Dynamic Switch
Logic
PLL
PLL_En
÷4
÷16
Qb0
Qb1
Qb2
Qa0
Qa1
MR
Man_Override
Clk_Selected
Inp1bad
Inp0bad
Alarm_Reset
OR
800 - 1600 MHz
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
MPC9892
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9893 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch |
| MPC9893AE | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893AER2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893FA | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 48-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9893FAR2 - Tape and Reel |
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