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參數(shù)資料
| 型號(hào)： | MPC9892FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 102K |
| 代理商： | MPC9892FA |
3
MPC9892
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
309
DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40° to +85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS control inputs (OE, FSEL0, FSEL1, MR)
VIL
Input voltage low
0.8
V
VIH
Input voltage high
2.0
V
IIN
Input Currentb
±TBD
A
VIN = VCC or VIN = GND
LVPECL clock inputs (CLK, CLK)c
VPP
AC differential input voltaged
0.1
1.3
V
Differential operation
VCMR
Differential cross point voltagee
1.0
VCC-0.3
V
Differential operation
VIH
Input high voltage
TBD
VIL
Input low voltage
TBD
IIN
Input Current
±TBD
A
VIN = TBD or VIN = TBD
LVPECL clock outputs (QA0-4, QA0-4, QB0-4, QB0-4)
VOH
Output High Voltage
TBD
VCC-1.005
TBD
V
Termination 50
W to VTT
VOL
Output Low Voltage
TBD
VCC-1.705
TBD
V
Termination 50
W to VTT
ICC
Maximum Power Supply
VCC pins
TBD
mA
ICCA
Maximum PLL Power Supply VCC_PLL pin
TBD
mA
a. AC characterisitics are design targets and pending characterization.
b. Input have internal pullup/pulldown resistors which affect the input current.
c. Clock inputs driven by LVPECL compatible signals.
d. VPP is the minimum differential input voltage swing required to maintain AC characteristic.
e. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
AC CHARACTERISTICS (TA = –40°C to 85°C, VCC = 3.3V ± 5%) (Note 5.)
Symbol
Parameter
Min
Typ
Max
Unit
fVCO
PLL VCO Lock Range
800
1600
MHz
25
75
%
tpd
Propagation Delay (Note 1.)
CLKn to Q (Bypass)
CLKn to Ext_FB (Locked (Note 2.))
TBD
ns
ps
VPP
Differential input voltage
(peak-to-peak)
0.3
1.3
V
VCMR
Differential input crosspoint voltage
VCC-0.3
V
tr/tf
Output Rise/Fall Time
TBD
ps
tskew
Output Skew
Within Bank
All Outputs
35
50
ps
pe
Maximum Phase Error Deviation
TBD (Note 3.)
TBD (Note 4.)
ps
per/cycle
Rate of Change of Periods
75MHz Output (Note 1., 3.)
300MHz Output (Note 1., 3.)
75MHz Output (Note 1., 4.)
300MHz Output (Note 1., 4.)
20
10
200
100
50
25
400
200
ps/cycle
tpw
Output Duty Cycle
45
55
%
tjitter
Cycle–to–Cycle Jitter, Standard Deviation (RMS)
(Note 1.)
20
ps
tlock
Maximum PLL Lock Time
10
ms
1. Guaranteed, not production tested.
2. Static phase offset between the selected reference clock and the feedback signal.
3. Specification holds for a clock switch between two signals no greater than 400ps out of phase. Delta period change per cycle is averaged over
the clock switch excursion. (See Applications Information section on page 310 for more detail)
4. Specification holds for a clock switch between two signals no greater than
±π out of phase. Delta period change per cycle is averaged over the
clock switch excursion.
5. PECL output termination is 50 ohms to VCC – 2.0V.
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