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參數(shù)資料
| 型號(hào)： | MPIC2131 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 3 HIGH SIDE & 3 LOW SIDE DRIVER |
| 中文描述： | 3高壓側(cè) |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | MPIC2131 |
3
Motorola Power Products Division Advanced Data
RECOMMENDED OPERATING CONDITIONS
The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended condi-
tions. The VS offset rating is tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage
VB1,2,3
VS1,2,3
VHO1,2,3
VCC
VLO1,2,3
VSS
VIN
FAULT–
VS1,2,3+10
Note 1
VS1,2,3+20
VSO+600
VB1,2,3
20
V
High Side Floating Supply Offset Voltage
V
High Side Floating Output Voltage
VS1,2,3
10
V
Fixed Supply Voltage
V
Low Side Output Voltage
0
VCC
5
V
Low Side Driver Return
–5
V
Logic Input Voltage (HIN–, LIN–, FLT–CLR, SD & ITRIP)
VSS
VSS
–40
5
V
Fault Output Voltage
VCC
125
V
Ambient Temperature
TA
°
C
Note 1: Logic operational for VS of –5 V to +600 V. Logic state held for VS of –5 V to –VBS.
ELECTRICAL CHARACTERISTICS
(TA = 25
°
C unless otherwise specified)
Characteristic
Symbol
Min
Typ
Max
Unit
STATIC ELECTRICAL CHARACTERISTICS
VBIAS (VCC, VBS1,2,3) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to COM and VSO1,2,3 and are applicable to
the respective output leads: HO1,2,3 or LO1,2,3.
Logic “0” Input Voltage (OUT = LO)
VIH
VIL
2.2
–
–
V
Logic “1” Input Voltage (OUT = HI)
–
–
0.8
V
Logic “0” Fault Clear Input Voltage
VFCLR,IH
VFCLR,IL
VSD,TH+
VSD,TH–
VIT,TH+
VIT,TH–
VOH
VOL
ILK
IQBS
IQCC
IIN+
IIN–
ITRIP+
ITRIP–
IFCLR+
IFCLR–
ISD+
ISD–
VBSUV+
VBSUV–
VCCUV+
VCCUV–
Ron,FLT
IO+
IO–
2.2
–
–
V
Logic “1” Fault Clear Input Voltage
–
–
0.8
V
SD Input Positive Going Threshold
–
1.8
–
V
SD Input Negative Going Threshold
–
1.5
–
V
ITRIP Input Positive Going Threshold
–
485
–
mV
ITRIP Input Negative Going Threshold
–
400
–
mV
High Level Output Voltage, VBIAS–VO @ VIN = 0 V, IO = 0 A
Low Level Output Voltage, VO @ VIN = 5 V, IO = 0 A
Offset Supply Leakage Current @ VB1,2,3 = VS1,2,3 = 600 V
Quiescent VBS Supply Current @ VIN = 0 V or 5 V
Quiescent VCC Supply Current @ VIN = 0 V or 5 V
Logic “1” Input Bias Current (OUT = HI) @ VIN = 0 V
Logic “0” Input Bias Current (OUT = LO) @ VIN = 5 V
“High” ITRIP Bias Current @ ITRIP = 5 V
–
–
100
mV
–
–
100
mV
–
–
50
μ
A
–
30
–
μ
A
–
3.0
–
mA
–
190
–
μ
A
–
100
–
μ
A
–
60
–
μ
A
“Low” ITRIP Bias Current @ ITRIP = 0 V
–
–
50
nA
Logic “1” Fault Clear Bias Current @ FLT–CLR = 0 V
–
190
–
μ
A
Logic “0” Fault Clear Bias Current @ FLT–CLR = 5 V
–
100
–
μ
A
Logic “1” Shut Down Bias Current @ SD = 5 V
–
60
–
μ
A
Logic “0” Shut Down Bias Current @ SD = 5 V
–
–
150
nA
VBS Supply Undervoltage Positive Going Threshold
VBS Supply Undervoltage Negative Going Threshold
VCC Supply Undervoltage Positive Going Threshold
VCC Supply Undervoltage Negative Going Threshold
FAULT – Low On Resistance
–
8.6
–
V
–
8.2
–
V
–
9.0
–
V
–
8.7
–
V
–
55
–
Output High Short Circuit Pulsed Current @ Vout = 0 V, Vin = 0 V, PW
≤
10
μ
s
Output Low Short Circuit Pulsed Current @ Vout = 15 V, Vin = 5 V, PW
≤
10
μ
s
200
250
–
mA
420
500
–
mA
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