270
2513L–AVR–03/2013
ATmega162/V
External Data Memory Timing
Notes:
1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Table 114. External Data Memory Characteristics, 4.5 - 5.5 Volts, no Wait-state
Symbol
Parameter
8 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/tCLCL
Oscillator Frequency
0.0
16
MHz
1tLHLL
ALE Pulse Width
115
1.0tCLCL-10
ns
2t
AVLL
Address Valid A to ALE Low
57.5
0.5t
ns
3a
tLLAX_ST
Address Hold After ALE Low,
write access
55
ns
3b
tLLAX_LD
Address Hold after ALE Low,
read access
55
ns
4tAVLLC
Address Valid C to ALE Low
57.5
ns
5t
AVRL
Address Valid to RD Low
115
1.0t
CLCL-10
ns
6tAVWL
Address Valid to WR Low
115
1.0tCLCL-10
ns
7tLLWL
ALE Low to WR Low
47.5
67.5
0.5tCLCL-15
0.5tCLCL+5
ns
8t
LLRL
ALE Low to RD Low
47.5
67.5
0.5t
CLCL-15
0.5t
CLCL+5
ns
9tDVRH
Data Setup to RD High
40
ns
10
tRLDV
Read Low to Data Valid
75
1.0tCLCL-50
ns
11
t
RHDX
Data Hold After RD High
0
ns
12
tRLRH
RD Pulse Width
115
1.0tCLCL-10
ns
13
t
DVWL
Data Setup to WR Low
42.5
0.5t
CLCL-20
ns
14
t
WHDX
Data Hold After WR High
115
1.0t
CLCL-10
ns
15
tDVWH
Data Valid to WR High
125
1.0tCLCL
ns
16
t
WLWH
WR Pulse Width
115
1.0t
CLCL-10
ns
Table 115. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state
Symbol
Parameter
8 MHz Oscillator
Variable Oscillator
Unit
Min
Max
Min
Max
01/t
CLCL
Oscillator Frequency
0.0
16
MHz
10
t
RLDV
Read Low to Data Valid
200
2.0t
CLCL-50
ns
12
tRLRH
RD Pulse Width
240
2.0tCLCL-10
ns
15
t
DVWH
Data Valid to WR High
240
2.0t
CLCL
ns
16
t
WLWH
WR Pulse Width
240
2.0t
CLCL-10
ns