149
2513L–AVR–03/2013
ATmega162/V
8-bit
Timer/Counter
Register
Description
Timer/Counter Control
Register – TCCR2
Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2 is written when
operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Compare
Match is forced on the Waveform Generation unit. The OC2 output is changed according to its
COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
Note:
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
However, the functionality and location of these bits are compatible with previous versions of
the timer.
Bit
7
6
5
4
3
210
FOC2
WGM20
COM21
COM20
WGM21
CS22
CS21
CS20
TCCR2
Read/Write
W
R/W
Initial Value
0
Table 60. Waveform Generation Mode Bit Description
Mode
WGM21
(CTC2)
WGM20
(PWM2)
Timer/Counter Mode
of Operation
TOP
Update of
OCR2 at
TOV2 Flag
Set on
0
Normal
0xFF
Immediate
MAX
1
0
1
PWM, Phase Correct
0xFF
TOP
BOTTOM
2
1
0
CTC
OCR2
Immediate
MAX
3
1
Fast PWM
0xFF
TOP
MAX