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參數(shù)資料
| 型號： | MQ80C52XXX-36/883:RD |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 6193K |
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20
2467X–AVR–06/11
ATmega128
Data Memory Access
Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU cycles as described in Figure 10.
Figure 10. On-chip Data SRAM Access Cycles
EEPROM Data
Memory
The Atmel AVRATmega128 contains 4Kbytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
“Memory Programming” on page 286 contains a detailed description on EEPROM programming
in SPI, JTAG, or Parallel Programming mode
EEPROM Read/Write
Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 2. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See “Prevent-
ing EEPROM Corruption” on page 24. for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
EEPROM Address
Register – EEARH and
EEARL
Bits 15..12 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Write
CPU
Memory access instruction
Next instruction
Bit
15141312
11
10
9
8
–
EEAR11
EEAR10
EEAR9
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7
654
3
2
1
0
Read/Write
RR
R/W
Initial Value
0
X
XXX
X
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