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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
188.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing
noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the
OCR1A Register, the ICR1 Register, or by a set of fixed values. When using OCR1A as TOP value in a PWM
mode, the OCR1A Register can not be used for generating a PWM output. However, the TOP value will in this
case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the
ICR1 Register can be used as an alternative, freeing the OCR1A to be used as PWM output.
16.2.2
Definitions
The following definitions are used extensively throughout the section:
16.2.3
Compatibility
The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Coun-
ter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding:
All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers
Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers
Interrupt Vectors
The following control bits have changed name, but have same functionality and register location:
PWM10 is changed to WGM10
PWM11 is changed to WGM11
CTC1 is changed to WGM12
The following bits are added to the 16-bit Timer/Counter Control Registers:
FOC1A and FOC1B are added to TCCR1C
WGM13 is added to TCCR1B
The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases.
16.3
Accessing 16-bit registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit
register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between
all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When
the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as
the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does
not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read
before the high byte.
Table 16-1.
Definition of Timer/Counter values.
BOTTOM
The counter reaches the BOTTOM when it becomes 0x0000.
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP
value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the
OCR1A or ICR1 Register. The assignment is dependent of the mode of operation.