
421
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
Figure 29-8. Programmable Delays
29.7.3.5
Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS
signals are high before and after each transfer.
Fixed Peripheral Select: SPI exchanges data with only one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the cur-
rent peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to reprogram
the NPCS field in the SPI_MR register.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the cur-
rent peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the
SPI_TDR register as the following format.
[xxxxxxx(7-bit) +
LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip
select to assert as defined in
Section 29.8.4 (SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending
on CSAAT bit.
Note:
1. Optional.
29.7.3.6
SPI Direct Access Memory Controller (DMAC)
In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to reduce processor
overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal
means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However,
changing the peripheral selection requires the Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the
Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the periph-
eral it is destined to. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred
through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of
memory size for the buffers, but it provides a very effective means to exchange data with several peripherals with-
out any intervention of the processor.
DLYBCS
DLYBS
DLYBCT
Chip Select 1
Chip Select 2
SPCK