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型號(hào)：	MQ83C154TXXX-L16P883
廠商：	TEMIC SEMICONDUCTORS
元件分類(lèi)：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	434/839頁(yè)
文件大?。?/td>	61013K
代理商：	MQ83C154TXXX-L16P883

ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]

8285E–AVR–02/2013

Register description

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction

AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the

Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the

Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as

early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can

be found by examining the Reset Flags.

WDTCR – Watchdog Timer Control Register

Bits 7:5 – Reserved

These bits are reserved and will always read as zero.

Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once

written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a

Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See ”Timed Sequences

Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the

Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an

enabled Watchdog Timer, the following procedure must be followed:

Initial Value

See Bit Description

Initial Value

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MQ83C154XXX-L16P883D	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
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