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型號(hào)：	MQ83C154TXXX-L16P883
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	73/839頁(yè)
文件大?。?/td>	61013K
代理商：	MQ83C154TXXX-L16P883

ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]

8285E–AVR–02/2013

Flushing the Receive Buffer

The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its con-

tents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error

condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows how to

flush the receive buffer.

Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The

clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchro-

nous serial frames at the RxD pin. The data recovery logic samples and low pass filters each incoming bit, thereby

improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the

accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 20-5 illustrates the sam-

pling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and

eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the synchronization variation

due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of

operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communication activity).

Figure 20-5. Start Bit sampling.

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection

sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic

then uses samples 8, 9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode (indicated with

sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three

samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver

Assembly code example

USART_Flush:

UCSR0A, RXC0

C code example

USART_Flush( void )

unsigned char

( UCSR0A & (1<<RXC0) ) dummy = UDR0;

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MR83C154TXXX-30/883D	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
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