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型號(hào)：	MR80C154-30P883R
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 30 MHz, MICROCONTROLLER, CQCC44
封裝：	LCC-44
文件頁(yè)數(shù)：	33/839頁(yè)
文件大?。?/td>	61013K
代理商：	MR80C154-30P883R

ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]

8285E–AVR–02/2013

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer

T2). clkT2 can be generated from an external or internal clock source, selected by the Clock Select bits

(CS2[2:0]). When no clock source is selected (CS2[2:0] = 0) the timer is stopped. However, the TCNT2 value can

be accessed by the CPU, regardless of whether clk

T2 is present or not. A CPU write overrides (has priority over) all

counter clear or count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter

Control Register (TCCR2A). There are close connections between how the counter behaves (counts) and how

waveforms are generated on the Output Compare output OC2A. For more details about advanced counting

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM2[1:0]

bits. TOV2 can be used for generating a CPU interrupt.

Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A). Whenever

TCNT2 equals OCR2A, the comparator signals a match. A match will set the Output Compare Flag (OCF2A) at the

next timer clock cycle. If enabled (OCIE2A = 1), the Output Compare Flag generates an Output Compare interrupt.

The OCF2A Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2A Flag can be

cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal

to generate an output according to operating mode set by the WGM2[1:0] bits and Compare Output mode

(COM2A[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special

cases of the extreme values in some modes of operation (”Modes of Operation” on page 130).

Figure 18-3 shows a block diagram of the Output Compare unit.

Figure 18-3. Output Compare Unit, block diagram.

The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the

Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buff-

ering synchronizes the update of the OCR2A Compare Register to either top or bottom of the counting sequence.

The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the

output glitch-free.

The OCR2A Register access may seem complex, but this is not case. When the double buffering is enabled, the

CPU has access to the OCR2A Buffer Register, and if double buffering is disabled the CPU will access the OCR2A

OCFnx (Int.Req.)

= (8-bit Comparator )

Waveform Generator

COMnx1:0

相關(guān)PDF資料	PDF描述
MR83C154TXXX-30/883D	8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
MD80C154-16P883	8-BIT, 16 MHz, MICROCONTROLLER, CDIP40
MD83C154TXXX-16P883D	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
MR83C154XXX-16P883D	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
MR80C154-20/883	8-BIT, 20 MHz, MICROCONTROLLER, CQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MR80C154-36	制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
MR80C154-L16	制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
MR80C31BH	制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space
MR80C31BH/B	制造商:n/a 功能描述:8506401XA
MR80C31BHB	制造商:n/a 功能描述:8506401XA

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