參數(shù)資料
型號： MR80C32-12P883D
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 68/91頁
文件大?。?/td> 19688K
代理商： MR80C32-12P883D
412
XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 33-50.Burst access within a single page
Figure 33-51.Burst access crossing page boundary
** NOP is only inserted for CAS3
**** The number of NOPs is equal to WRDLY[1:0] + 1 (WRDLY = 0 is shown)
***** The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown)
* The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
*** Clock suspended for 1 cycle when EBI is running at 1x and 1 or 2 cycles when EBI
is running at 2x, to enable sampling of data on the positive edge of the 1x clock.
Bank Adr
Row Adr
Col Adr
Burst access within a single page
0x0
Col Adr
0x400
Col Adr
P
recha
rg
eA
ll
Bank
s
Ac
tive
Re
a
d
NO
P*
NO
P
***
*
D
ata
s
a
m
ple
d
NO
P**
Cl
ock
su
spend
**
*
Re
a
d
D
ata
s
a
m
ple
d
NO
P**
Cl
ock
su
spend
**
*
Re
a
d
D
ata
s
a
m
ple
d
NO
P**
Cl
ock
su
spend
**
*
D[3:0]
D[7:4]
D
ata
s
a
m
ple
d
Cl
ock
susp
en
d
D
ata
s
a
m
ple
d
Cl
ock
susp
en
d
D[3:0]
D[7:4]
D[3:0]
D[7:4]
D
ata
s
a
m
ple
d
Cl
ock
susp
en
d
CLK
CKE
CAS
RAS
DQM
BA[1:0]
A[11:0]
D
ClkPER2
WE
CS
** NOP is only inserted for CAS3
**** The number of NOPs is equal to WRDLY[1:0] + 1 (WRDLY = 0 is shown)
***** The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown)
* The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
*** Clock suspended for 1 cycle when EBI is running at 1x and 1 or 2 cycles when EBI
is running at 2x, to enable sampling of data on the positive edge of the 1x clock.
Burst access crossing page boundary
Bank Adr
Row Adr
Col Adr
0x0
Col Adr
0x400
Col Adr
P
re
char
ge
A
ll
B
anks
Ac
tiv
e
Re
ad
NOP
*
NO
P*
***
D
ata
s
am
p
le
d
NOP
**
Cl
oc
k
su
sp
en
d*
**
Re
ad
D
ata
s
am
p
le
d
NOP
**
Cl
oc
k
su
sp
en
d*
**
Re
ad
D
ata
s
am
p
le
d
NOP
**
Cl
oc
k
su
sp
en
d*
**
0x400
0x0
Bank Adr
P
re
char
ge
A
ll
B
anks
NO
P*
***
*
Ac
tiv
e
NOP
*
D[3:0]
D[7:4]
D
ata
s
am
p
le
d
Cl
ock
su
spend
D[3:0]
D[7:4]
D[3:0]
D[7:4]
D
ata
s
am
p
le
d
Cl
ock
su
spend
D
ata
s
am
p
le
d
Cl
ock
su
spend
CLK
CKE
CAS
RAS
DQM
BA[1:0]
A[11:0]
D
ClkPER2
WE
CS
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