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參數(shù)資料
| 型號： | MR80C32-20/883:D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 57/103頁 |
| 文件大?。?/td> | 25028K |
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15
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
7.5.1
SPH and SPL – Stack Pointer High and Stack pointer Low
Note:
1. Initial values respectively for the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P.
7.5.2
RAMPZ – Extended Z-pointer Register for ELPM/SPM
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown
in Figure 7-4 on page 15. Note that LPM is not affected by the RAMPZ setting.
Figure 7-4.
The Z-pointer used by ELPM and SPM.
The actual number of bits is implementation dependent. Unused bits in an implementation will
always read as zero. For compatibility with future devices, be sure to write these bits to zero.
Note:
1. RAMPZ is only valid for ATmega1284/ATmega1284P.
7.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
CPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 7-5 on page 16 shows the parallel instruction fetches and instruction executions enabled
by the Harvard architecture and the fast-access Register File concept. This is the basic pipelin-
ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Bit
151413121110
9
8
–
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
765
432
10
Read/Write
R
R/W
Initial Value
0
0/1
1/0
00
111
11
Table 7-2.
Stack Pointer size
Device
Stack Pointer size
ATmega164A/ATmega164PA
SP[10:0]
ATmega324A/ATmega324PA
SP[11:0]
ATmega644A/ATmega644PA
SP[12:0]
ATmega1284/ATmega1284P
SP[13:0]
Bit
7
65432
1
0
RAMPZ7
RAMPZ6
RAMPZ5
RAMPZ4
RAMPZ3
RAMPZ2
RAMPZ1
RAMPZ0
RAMPZ
Read/Write
R/W
Initial Value
0
00000
0
Bit (Individually)
7
0
7
0
7
0
RAMPZ
ZH
ZL
Bit (Z-pointer)
23
16
15
8
7
0
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