![](http://datasheet.mmic.net.cn/30000/MR80C32-20-D_datasheet_2377239/MR80C32-20-D_114.png)
114
8154B–AVR–07/09
ATmega16A
ensure that both the high and Low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
16.11.4
OCR1AH and OCR1AL – Output Compare Register 1 A
16.11.5
OCR1BH and OCR1BL – Output Compare Register 1 B
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and Low bytes
are written simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the
16.11.6
ICR1H and ICR1L – Input Capture Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the analog comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and Low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
Bit
765
432
10
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
Read/Write
R/W
Initial Value
0
Bit
765
432
10
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
Read/Write
R/W
Initial Value
0
Bit
765
432
10
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
Read/Write
R/W
Initial Value
0