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參數(shù)資料
| 型號： | MR80C52CXXX-12SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 48/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MR80C52CXXX-12SHXXX |
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248
XMEGA A [MANUAL]
8077I–AVR–11/2012
21.15.5 CTRLC – Control register C
Note:
1. Master SPI mode
Bits 7:6 – CMODE[1:0]: Communication Mode
These bits select the mode of operation of the USART as shown in Table 21-7.
Table 21-7.
CMODE bit settings.
Notes:
1.
See “IRCOM – IR Communication Module” on page 252 for full description on using IRCOM mode.
2.
See “USART in Master SPI Mode” on page 243 for full description of the master SPI operation.
Bits 5:4 – PMODE[1:0]: Parity Mode
These bits enable and set the type of parity generation according to Table 21-8 on page 248. When enabled, the
transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The receiver will
generate a parity value for the incoming data and compare it to the PMODE setting, and if a mismatch is detected, the
PERR flag in STATUS will be set.
These bits are unused in master SPI mode operation.
Table 21-8. PMODE bit settings.
Bit 3 – SBMODE: Stop Bit Mode
This bit selects the number of stop bits to be inserted by the transmitter according to Table 21-9. The receiver ignores
this setting.
This bit is unused in master SPI mode operation
Bit
7654
3210
+0x05
CMODE[1:0]
PMODE[1:0]
SBMODE
CHSIZE[2:0]
+0x05(1)
CMODE[1:0]
–
UDORD
UCPHA
–
Read/Write
R/W
Initial Value
0
1
0
CMODE[1:0]
Group configuration
Mode
00
ASYNCHRONOUS
Asynchronous USART
01
SYNCHRONOUS
Synchronous USART
10
IRCOM
IRCOM(1)
11
MSPI
Master SPI(2)
PMODE[1:0]
Group configuration
Parity Mode
00
DISABLED
Disabled
01
–
Reserved
10
EVEN
Enabled, even parity
11
ODD
Enabled, odd parity
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