- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25639 > MR80C52CXXX-12SHXXX (ATMEL CORP) 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 PDF資料下載
參數(shù)資料
| 型號： | MR80C52CXXX-12SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 66/80頁 |
| 文件大小： | 5152K |
| 代理商： | MR80C52CXXX-12SHXXX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁當前第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
266
XMEGA A [MANUAL]
8077I–AVR–11/2012
24.5.3 Multiplexing address byte 0 and 2
When address byte 0 (A[7:0]) and address byte 2 (A[23:16) are multiplexed, they are output from the same port, and the
ALE2 signal from the device controls the address latch.
Figure 24-5. Multiplexed SRAM connection using ALE2.
24.5.4 Multiplexing address byte 0, 1and 2
When address byte 0 (A[7:0]), address byte 1 (A[15:8]) and address byte 2 (A[23:16] are multiplexed, they are output
from the same port, and the ALE1 and ALE2 signal from the device control the external address latches.
Figure 24-6. Multiplexed SRAM connection using ALE1 and ALE2.
24.5.5 Address Latches
The Address Latch timing and parameter requirements are described in EBI Timing. See the device datasheet
characteristics for details. To reduce access time when using multiplexing of address, the ALE signals are only issued
when it is required to update the latched address. For instance if address lines A[15:8] are multiplexed with A[7:0] the
ALE1 and A[15:8] are only given if any bit in A[15:8] are changed since the last access.
24.5.6 Timing
SRAM or external memory devices may have different timing requirements. To meet these varying requirements, each
Chip Select can be configured with different wait-states. Timing details are described in the device datasheet.
24.6
SRAM LPC Configuration
The SRAM Low Pin Count (LPC) configuration enables EBI to be configured for multiplexing modes where the data and
address lines are multiplexed. Compared to SRAM configuration, this can further reduce the number of pins required for
EBI
SRAM
D[7:0]
A[23:16]/
A[7:0]
ALE2
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[23:16]
A[15:8]
EBI
SRAM
D[7:0]
A[23:16]/
A[15:8]/
A[7:0]
ALE1
ALE2
D
Q
G
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[23:16]
相關PDF資料 |
PDF描述 |
|---|---|
| MC80C52CXXX-12SB | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C32-25SCD | 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C32E-20SHXXX:D | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52CXXX-16SCD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MF180C51-16R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復。