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參數(shù)資料
| 型號： | MR80C52CXXX-36/883:R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 122/142頁 |
| 文件大小： | 25028K |
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208
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
20.8
Register description
The following section describes the registers used for SPI operation using the USART.
20.8.1
UDRn – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to
normal USART operation. See “UDRn – USART I/O Data Register n” on page 193.
20.8.2
UCSRnA – USART MSPIM Control and Status Register n A
Bit 7 – RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (that is, does not contain any unread data). If the Receiver is disabled, the
receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag
can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
Bit 6 – TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
Bit 4:0 – Reserved in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
20.8.3
UCSRnB – USART MSPIM Control and Status Register n B
Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
Bit
7
6
5
4
3
2
1
0
RXCn
TXCn
UDREn
–
UCSRnA
Read/Write
R/W
R
Initial Value
0
1
0
Bit
7
6
5
4
3
210
RXCIEn
TXCIEn
UDRIE
RXENn
TXENn
–
UCSRnB
Read/Write
R/W
R
Initial Value
0
1
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR80C52EXXX-16SHXXX:RD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| MQ80C32-12SHXXX:D | 8-BIT, 12 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C32-20SHXXX:RD | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| MC80C52CXXX-36:D | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
| MC80C52XXX-36/883:D | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
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| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
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| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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