參數(shù)資料
型號: MR80C52CXXX-36/883:R
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 131/142頁
文件大?。?/td> 25028K
216
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 21-8. Arbitration between two masters.
Note that arbitration is not allowed between:
A REPEATED START condition and a data bit
A STOP condition and a data bit
A REPEATED START and a STOP condition
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composi-
tion of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
START
Master A Loses
Arbitration, SDA
A
SDA
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