參數(shù)資料
型號: MR80C52EXXX-36SHXXX:D
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 60/91頁
文件大?。?/td> 19688K
405
XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 33-43.Burst access crossing page boundary
** NOP is only inserted for CAS3
**** The number of NOPs is equal to WRDLY[1:0] + 1 (WRDLY = 0 is shown)
***** The number of NOPs is equal to RPDLY[1:0] (RPDLY = 1 is shown)
* The number of NOPs is equal to ROWCOLDLY[2:0] (ROWCOLDLY = 1 is shown)
*** Clock suspended for 1 cycle when EBI is running at 1x and 1 or 2 cycles when EBI
is running at 2x, to enable sampling of data on the positive edge of the 1x clock.
Burst access crossing page boundary
Bank Adr
Row Adr
Col Adr
0x0
Col Adr
0x400
Col Adr
D[7:0]
Pr
ec
ha
rg
eAl
lBa
nk
s
Ac
tiv
e
Rea
d
NOP
*
N
O
P*
***
D
a
ta
samp
le
d
NOP
**
C
lock
su
spen
d*
**
Rea
d
D
a
ta
samp
le
d
NOP
**
C
lock
su
spen
d*
**
Rea
d
D
a
ta
samp
le
d
NOP
**
C
lock
su
spen
d*
**
0x400
0x0
Bank Adr
Pr
ec
ha
rg
eAl
lBa
nk
s
N
O
P*
***
*
Ac
tiv
e
NOP
*
CLK
CKE
CAS
RAS
DQM
BA[1:0]
A[11:0]
D
ClkPER2
WE
CS
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