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    • 參數(shù)資料
      型號(hào): MR80C52TXXX-30SBD
      廠商: ATMEL CORP
      元件分類: 微控制器/微處理器
      英文描述: 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
      封裝: LCC-44
      文件頁(yè)數(shù): 141/141頁(yè)
      文件大?。?/td> 7628K
      代理商: MR80C52TXXX-30SBD
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      9
      8151H–AVR–02/11
      ATmega128A
      6.
      AVR CPU Core
      6.1
      Introduction
      This section discusses the AtmelAVR core architecture in general. The main function of the
      CPU core is to ensure correct program execution. The CPU must therefore be able to access
      memories, perform calculations, control peripherals and handle interrupts.
      6.2
      Architectural Overview
      Figure 6-1.
      Block Diagram of the AVR Architecture
      In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
      separate memories and buses for program and data. Instructions in the program memory are
      executed with a single level pipelining. While one instruction is being executed, the next instruc-
      tion is pre-fetched from the program memory. This concept enables instructions to be executed
      in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
      The fast-access Register file contains 32 × 8-bit general purpose working registers with a single
      clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
      ical ALU operation, two operands are output from the Register file, the operation is executed,
      and the result is stored back in the Register file – in one clock cycle.
      Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
      Space addressing – enabling efficient address calculations. One of the these address pointers
      Flash
      Program
      Memory
      Instruction
      Register
      Instruction
      Decoder
      Program
      Counter
      Control Lines
      32 x 8
      General
      Purpose
      Registrers
      ALU
      Status
      and Control
      I/O Lines
      EEPROM
      Data Bus 8-bit
      Data
      SRAM
      Direct
      Addressing
      Indirect
      Addressing
      Interrupt
      Unit
      SPI
      Unit
      Watchdog
      Timer
      Analog
      Comparator
      I/O Module 2
      I/O Module1
      I/O Module n
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