參數(shù)資料
型號: MR80C52TXXX-30SBD
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
封裝: LCC-44
文件頁數(shù): 50/141頁
文件大?。?/td> 7628K
代理商: MR80C52TXXX-30SBD
228
8021G–AVR–03/11
ATmega329P/3290P
22.9.3
ADCL and ADCH – The ADC Data Register
22.9.3.1
ADLAR = 0
22.9.3.2
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers. When ADCL is
read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left
adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise,
ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on
22.9.4
ADCSRB – ADC Control and Status Register B
101
32
110
64
111
128
Table 22-5.
ADC Prescaler Selections (Continued)
ADPS2
ADPS1
ADPS0
Division Factor
Bit
1514
131211
10
9
8
ADC9
ADC8
ADCH
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
76
543
210
Read/Write
R
RRR
R
RRR
R
Initial Value
0
00
000
Bit
1514
1312
1110
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
ADCL
76
54
32
10
Read/Write
RR
Initial Value
0
00
Bit
7
65
43
2
1
0
ACME
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R
R/W
R
R/W
Initial Value
0
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