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參數(shù)資料
| 型號： | MR80C52XXX-36/883:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 3152K |
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18
7707F–AVR–11/10
AT90USB82/162
The 32 general purpose working registers, 64 I/O registers, and the 512 bytes of internal data
SRAM in the AT90USB82/162 are all accessible through all these addressing modes. The Reg-
ister File is described in “General Purpose Register File” on page 11.
Figure 5-2.
Data Memory Map
5.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU cycles as described in Figure 5-3.
Figure 5-3.
On-chip Data SRAM Access Cycles
5.3
EEPROM Data Memory
The AT90USB82/162 contains 512 bytes of data EEPROM memory. It is organized as a sepa-
rate data space, in which single bytes can be read and written. The EEPROM has an endurance
of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is
described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg-
ister, and the EEPROM Control Register.
32 R
egisters
64 I/O
R
egisters
I
nternal S RAM
(512
x 8)
$0000 - $001F
$0020 - $005F
$2FF
$0060 - $00FF
D
ata Memory
160 E
xt I/O
R
eg.
$0100
clk
WR
RD
Data
Address
Address valid
T1
T2
T3
Compute Address
Read
Wr
ite
CPU
Memory Access Instruction
Next Instruction
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