參數(shù)資料
型號(hào)： MR80C52XXX-36/883:RD
廠商： TEMIC SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
文件頁(yè)數(shù)： 6/32頁(yè)
文件大?。?/td> 3152K
13
7707F–AVR–11/10
AT90USB82/162
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 4-5.
Single Cycle ALU Operation
4.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 63. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 63 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
clk
CPU
相關(guān)PDF資料
PDF描述
MC80C52EXXX-36:D 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40
MV80C51T-25D 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQFP44
MR83C154TXXX-36P883D 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
MT80C51C-16D 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
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