參數(shù)資料
型號: MR83C154XXX-16P883
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
封裝: LCC-44
文件頁數(shù): 133/142頁
文件大?。?/td> 61013K
代理商: MR83C154XXX-16P883
90
XMEGA B3 [DATASHEET]
8074D–AVR–08/2013
36.16 Two-Wire Interface Characteristics
Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface
meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7.
Figure 36-7. Two-Wire Interface Bus Timing
Table 36-30. Two wire serial bus characteristics.
tHD;STA
tof
SDA
SCL
tLOW
tHIGH
tSU;STA
tBUF
tr
tHD;DAT
tSU;DAT
tSU;STO
Symbol
Parameter
Condition
Min
Typ
Max
Units
V
IH
Input High Voltage
0.7*V
CC
V
CC+0.5
V
IL
Input Low Voltage
-0.5
0.3*V
CC
Vhys
Hysteresis of Schmitt Trigger Inputs
0.05VCC(1)
0
V
OL
Output Low Voltage
3mA, sink current
0
0.4
t
r
Rise Time for both SDA and SCL
20+0.1C
b
300
ns
tof
Output Fall Time from VIHmin to VILmax
10pF < Cb < 400pF(2)
20+0.1Cb(1)(2)
250
tSP
Spikes Suppressed by Input Filter
0
50
I
Input Current for each I/O Pin
0.1V
CC < VI < 0.9VCC
-10
10
A
CI
Capacitance for each I/O Pin
10
pF
fSCL
SCL Clock Frequency
fPER(3)>max(10fSCL, 250kHz)
0
400
kHz
RP
Value of Pull-up resistor
f
SCL 100kHz
fSCL > 100kHz
tHD;STA
Hold Time (repeated) START condition
fSCL 100kHz
4.0
s
f
SCL > 100kHz
0.6
t
LOW
Low Period of SCL Clock
fSCL 100kHz
4.7
s
fSCL > 100kHz
1.3
tHIGH
High Period of SCL Clock
f
SCL 100kHz
4.0
s
fSCL > 100kHz
0.6
t
SU;STA
Set-up time for a repeated START condition
fSCL 100kHz
4.7
s
f
SCL > 100kHz
0.6
t
HD;DAT
Data hold time
f
SCL 100kHz
0
3.5
s
fSCL > 100kHz
0
0.9
V
CC
0.4V
3mA
----------------------------
100ns
C
b
---------------
300ns
C
b
---------------
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