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參數(shù)資料
| 型號： | MR83C154XXX-16P883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 73/142頁 |
| 文件大小： | 61013K |
| 代理商： | MR83C154XXX-16P883 |
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36
XMEGA B3 [DATASHEET]
8074D–AVR–08/2013
17.
TC2 –16-bit Timer/Counter Type 2
17.1
Features
A system of two eight-bit timer/counters
Low-byte timer/counter
High-byte timer/counter
Eight compare channels
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
Can be used to trigger DMA transactions
High-resolution extension increases frequency and waveform resolution by 4x or 8x
17.2
Overview
A timer/counter 2 is realized when a timer/counter 0 is set in split mode. It is a system of two eight-bit timer/counters,
each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with
individually controlled duty cycles, and is intended for applications that require a high number of PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts, events and DMA triggers.
The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be
clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always
counting down.
The timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one timer/counter can exist only as
either type 0 or type 2.
PORTC has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2).
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