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參數資料
| 型號： | MR83C154XXX-25/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數： | 5/141頁 |
| 文件大小： | 7628K |
| 代理商： | MR83C154XXX-25/883D |
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14
2486AA–AVR–02/2013
ATmega8(L)
Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 5. The Parallel Instruction Fetches and Instruction Executions
Figure 6 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6. Single Cycle ALU Operation
Reset and
Interrupt Handling
The Atmel
AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate Program Vector in the Program memory space. All inter-
rupts are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on
the Program Counter value, interrupts may be automatically disabled when Boot Lock Bits
BLB02 or BLB12 are programmed. This feature improves software security. See the section
“Memory Programming” on page 215 for details.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 46. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Inter-
rupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to
“Interrupts” on page 46 for more information. The Reset Vector can also be moved to the start of
the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
clk
CPU
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| MR83C154CXXX-25P883R | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44 |
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| MR80C52EXXX-12/883:R | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MR80C52XXX-12 | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| MF180C51T-12D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
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