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參數(shù)資料
| 型號： | MS80C51-12D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 56/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MS80C51-12D |
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XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 23-1. Register file usage during DES encryption/decryption.
Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be executed in increasing
order to form the correct DES ciphertext or plaintext. Intermediate results are stored in the register file (R0-R15) after
each DES instruction. After sixteen rounds, the key is located in R8-R16 and the encrypted/decrypted ciphertext/plaintext
is located in R0-R7. The instruction's operand (K) determines which round is executed, and the half carry flag (H) in the
CPU status register determines whether encryption or decryption is performed. If the half carry flag is set, decryption is
performed, and if the flag is cleared, encryption is performed.
For more details on the DES instruction, refer to the AVR instruction set manual.
23.4
AES Crypto Module
The AES crypto module performs encryption and decryption according to the Advanced Encryption Standard (FIPS-197).
The 128-bit key block and 128-bit data block (plaintext or ciphertext) must be loaded into the key and state memories in
the AES crypto module. This is done by writing the AES KEY register and STATE register sequentially with 16 bytes.
It is software selectable whether the module should perform encryption or decryption. It is also possible to enable XOR
mode, where all new data loaded to the state key is XORed with the current data in the state memory.
The AES module uses 375 clock cycles before the encrypted/decrypted plaintext/ciphertext is available for readout in the
state memory.
The following setup and use procedure is recommended:
1.
Enable the AES interrupt (optional).
2.
Select the AES direction to encryption or decryption.
3.
Load the key data block into the AES key memory.
4.
Load the data block into the AES state memory.
5.
Start the encryption/decryption operation.
If more than one block is to be encrypted or decrypted, repeat the procedure from step 3.
When the encryption/decryption procedure is complete, the AES interrupt flag is set and an optional interrupt is
generated.
Register File
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
...
R31
data0
data1
data2
data3
data4
data5
data6
data7
key0
key1
key2
key3
key4
key5
key6
key7
data
key
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