參數(shù)資料
型號(hào): MSC7112VM1000
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 42/56頁(yè)
文件大?。?/td> 0K
描述: DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝: 90
系列: StarCore
類型: 定點(diǎn)
接口: 主機(jī)接口,I²C,UART
時(shí)鐘速率: 266MHz
非易失內(nèi)存: ROM(8 kB)
芯片上RAM: 208kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.20V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 400-LFBGA
供應(yīng)商設(shè)備封裝: 400-MAPBGA(17x17)
包裝: 托盤
Hardware Design Considerations
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
47
3.3.2
Peripheral Power
Peripherals include the DDR memory controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, and the I
2C module.
Basic power consumption by each module is assumed to be the same and is computed by using the following equation which
assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 100 MH or 133 MHz. This yields:
PPERIPHERAL = 20 pF × (1.2 V)
2 × 100 MHz × 10–3 = 2.88 mW per peripheral
Eqn. 7
PPERIPHERAL = 20 pF × (1.2 V)
2
× 133 MHz × 10–3 = 3.83 mW per peripheral
Eqn. 8
Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.
3.3.3
External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7112
device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.
The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
PDDRIO = PSTATIC + PDYNAMIC
Eqn. 9
PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V
Eqn. 10
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)
2
× 200 MHz × 10–3 mW
Eqn. 11
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)
2
× 266 MHz × 10–3 mW
Eqn. 12
pin activity value = (active data lines
× % activity × % data switching) + (active address lines × % activity)
Eqn. 13
As an example, assume the following:
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)
2 × 200 × 10–3) = 324.2 mW
Eqn. 14
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)
2
× 266 × 10–3) = 326.3 mW
Eqn. 15
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