參數(shù)資料
型號(hào)： MSC7116VF1000
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 37/60頁(yè)
文件大?。?/td> 0K
描述： DSP 16BIT W/DDR CTRLR 400-MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： StarCore
類型： 定點(diǎn)
接口： 主機(jī)接口，I²C，UART
時(shí)鐘速率： 266MHz
非易失內(nèi)存： ROM（8 kB）
芯片上RAM： 400kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應(yīng)商設(shè)備封裝： 400-MAPBGA（17x17）
包裝： 托盤
MSC7116 Data Sheet, Rev. 13
Hardware Design Considerations
Freescale Semiconductor
42
3.2
This section outlines the MSC7116 power considerations: power supply, power sequencing, power planes, decoupling, power
supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power
consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.
3.2.1
Power Supply
The MSC7116 requires four input voltages, as shown in Table 32.
You should supply the MSC7116 core voltage via a variable switching supply or regulator to allow for compatibility with
possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across VDDC
and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and reference voltages supply
the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM and GND. The reference voltage
is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 × VDDM. Refer to the JEDEC standard JESD8
(Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements.
3.2.2
Power Sequencing
One consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied.
The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is
extremely important to observe the power up and power down sequences at the board level to avoid latch-up, forward biasing
of ESD devices, and excessive currents, which all lead to severe device damage.
Note:
There are five possible power-up/power-down sequence cases. The first four cases listed in the following sections are
recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated
for current spike risks based on actual information for the specific application.
Table 32. MSC7116 Voltages
Voltage
Symbol
Value
Core
VDDC
1.2 V
Memory
VDDM
2.5 V
Reference
VREF
1.25 V
I/O
VDDIO
3.3 V
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