參數(shù)資料
型號(hào)： MSC8103M1200F
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù)： 30/120頁
文件大?。?/td> 1952K
代理商： MSC8103M1200F
1-13
System Bus, HDI16, and Interrupt Signals
Reserved
DP0
EXT_BR2
Input
Input/Output
Input
The primary configuration is reserved.
Data Parity 0
1
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity zero pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 0 and D[0–7].
External Bus Request 21,2
An external master asserts this pin to request bus ownership from the internal
arbiter.
IRQ1
DP1
EXT_BG2
Input
Input/Output
Output
Interrupt Request 11
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 1
1
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity one pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 1 and D[8–15].
External Bus Grant 21,2
The MSC8103 asserts this pin to grant bus ownership to an external bus master.
IRQ2
DP2
EXT_DBG2
Input
Input/Output
Output
Interrupt Request 21
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 21
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity two pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 2 and D[16–23].
External Data Bus Grant 21,2
The MSC8103 asserts this pin to grant data bus ownership to an external bus
master.
IRQ3
DP3
EXT_BR3
Input
Input/Output
Input
Interrupt Request 31
One of eight external lines that can request a service routine, via the internal
interrupt controller, from the SC140 core.
Data Parity 31
The agent that drives the data bus also drives the data parity signals. The value
driven on the data parity three pin should give odd parity (odd number of ones) on
the group of signals that includes data parity 3 and D[24–31].
External Bus Request 31,2
An external master asserts this pin to request bus ownership from the internal
arbiter.
Table 1-5.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Description
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