參數(shù)資料
型號(hào)： MSC8103M1200F
廠商： MOTOROLA INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, FLIP-CHIP, PLASTIC, BGA-332
文件頁數(shù)： 39/120頁
文件大?。?/td> 1952K
代理商： MSC8103M1200F
1-21
Communications Processor Module (CPM) Ports
PA25
FCC1: TXD0
UTOPIA
SDMA: MSNUM0
Output
FCC1: UTOPIA Transmit Data Bit 0
In the ATM UTOPIA interface supported by FCC1. The
MSC8103 outputs ATM cell octets (UTOPIA interface data)
on TXD[0–7]. TXD7 is the most significant bit. TXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes.
Module Serial Number Bit 0
MSNUM[0–4] of is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates
which section, transmit (0) or receive (1), is active during
the transfer.
PA24
FCC1: TXD1
UTOPIA
SDMA: MSNUM1
Output
FCC1: UTOPIA Transmit Data Bit 1
In the ATM UTOPIA interface supported by FCC1. The
MSC8103 outputs ATM cell octets (UTOPIA interface data)
on TXD[0–7]. TXD7 is the most significant bit. TXD0 is the
least significant bit. When no ATM data is available, idle
cells are inserted. A cell is 53 bytes.
Module Serial Number Bit 1
MSNUM[0–4] of is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates
which section, transmit (0) or receive (1), is active during
the transfer.
PA23
FCC1: TXD2
UTOPIA
Output
FCC1: UTOPIA Transmit Data Bit 2
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
PA22
FCC1: TXD3
UTOPIA
Output
FCC1: UTOPIA Transmit Data Bit 3
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
PA21
FCC1: TXD4
UTOPIA
FCC1: TXD3
MII and HDLC nibble
Output
FCC1: UTOPIA Transmit Data Bit 4
TXD[0–7] is part of the ATM UTOPIA interface supported by
FCC1. The MSC8103 outputs ATM cell octets (UTOPIA
interface data) on TXD[0–7]. TXD7 is the most significant
bit. TXD0 is the least significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes.
FCC1: MII and HDLC Nibble Transmit Data Bit 3
TXD[3–0] supports MII and HDLC nibble modes in FCC1.
TXD3 is the most significant bit. TXD0 is the least significant
bit.
Table 1-7. Port A Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose
I/O
Peripheral Controller:
Dedicated Signal
Protocol
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MSC8103RM/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor
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MSC8103VT1200F 功能描述:IC DSP 16BIT 300MHZ 332-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
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MSC81090 制造商:ASI 制造商全稱:ASI 功能描述:NPN SILICON RF POWER TRANSISTOR
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