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參數(shù)資料
| 型號(hào)： | MSC8122TVT6400 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 32-BIT, 400 MHz, OTHER DSP, PBGA431 |
| 封裝： | LEAD FREE, FCBGA-431 |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 1158K |
| 代理商： | MSC8122TVT6400 |
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MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freescale Semiconductor
16
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50
Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
Output Buffer Impedances
2.5.2
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8122 device:
PORESET
and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.
If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD
CLKIN
should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET
CLKIN
must not be pulled high during VDDH power-up. CLKIN can toggle during this period.
Note:
See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design
recommendations.
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are
raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises.
Figure 5. Overshoot/Undershoot Voltage for VIH and VIL
Table 6. Output Buffer Impedances
Output Buffers
Typical Impedance (
Ω)
System bus
50
Memory controller
50
Parallel I/O
50
Note:
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
GND
GND – 0.3 V
GND – 0.7 V
VIL
VIH
Must not exceed 10% of clock period
VDDH + 17%
VDDH + 8%
VDDH
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相關(guān)代理商/技術(shù)參數(shù) |
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| MSC8122TVT6400V | 功能描述:IC DSP QUAD 16B 400MHZ 431FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| MSC8122VT8000 | 功能描述:IC DSP QUAD 16B 500MHZ 431FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| MSC81250M | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS AVIONICS APPLICATIONS |
| MSC8126 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Digital Signal Processor |
| MSC8126_08 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Digital Signal Processor |
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