參數(shù)資料
型號(hào): MSC8144ESVT1000B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 50/80頁
文件大小: 1251K
代理商: MSC8144ESVT1000B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
54
2.6.9
Timer Timing
Figure 23 shows the timer input AC timing
2.6.10
Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144E
Reference Manual.
2.6.10.1
Management Interface Timing
Table 39. Timer Timing
Characteristics
Symbol
Min
Unit
TIMERx frequency
TTMREFCLK
10.0
ns
TIMERx Input high phase
TTMCH
4.0
ns
TIMERx Output low phase
TTMCL
4.0
ns
Figure 23. Timer Timing
Table 40. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
ETHMDC to ETHMDIO delay2
tMDKHDX
10
70
ns
ETHMDIO to ETHMDC rising edge setup time
tMDDVKH
7—
ns
ETHMDC rising edge to ETHMDIO hold time
tMDDXKH
0—
ns
Notes:
1.
Program the ETHMDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz, to
achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8144E Reference Manual for
configuration details.
2.
The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
TTMREFCLK
TTMCL
TTMCH
TIMERx (Input)
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