參數(shù)資料
型號(hào): MSC8144ESVT1000B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁(yè)數(shù): 53/80頁(yè)
文件大小: 1251K
代理商: MSC8144ESVT1000B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
57
Figure 28 shows the RMII transmit and receive AC timing diagram.
Figure 29 provides the AC test load.
2.6.10.5
SMII AC Timing Specification
Figure 30 shows the SMII Mode signal timing.
Figure 28. RMII Transmit and Receive AC Timing
Figure 29. AC Test Load
Table 44. SMII Mode Signal Timing
Characteristics
Symbol
Min
Max
Unit
ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge setup time
tSMDVKH
1.5
ns
ETHCLOCK rising edge to ETHSYNC_IN, ETHRXD hold time
tSMDXKH
1.0
ns
ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay
tSMXR
1.5
5.0
ns
Notes:
1.
Typical REF_CLK clock period is 8ns
2.
Measured using a 5 pF load.
3.
Measured using a 15 pF load
4.
Program GCR4 as 0x00002008
REF_CLK
TXD[1–0]
tRMTKHDX
tRMX
tRMXH
tRMXR
tRMXF
TX_EN
RXD[1–0]
tRMRDXKH
CRS_DV
RX_ER
tRMRDVKH
Valid Data
Output
Z0 = 50 Ω
VDDGE/2
RL = 50 Ω
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