參數(shù)資料
型號: MSC8144ETVT800B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 32/80頁
文件大?。?/td> 1251K
代理商: MSC8144ETVT800B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Electrical Characteristics
Freescale Semiconductor
38
See also Reset Errata for PLL lock and reset duration.
2
Delay from de-assertion of external PORESET to HRESET deassertion for
external pins and hard coded RCW
33 MHz <= CLKIN < 66 MHz
66 MHz <= CLKIN <= 133 MHz
Delay from de-assertion of external PORESET to HRESET deassertion for
loading RCW the I2C interface
33 MHz <= CLKIN < 44 MHz
44 MHz <= CLKIN < 66 MHz
66 MHz <= CLKIN < 100 MHz
100 MHz <= CLKIN < 133 MHz
15369/CLKIN
34825/CLKIN
92545/CLKIN
107435/CLKIN
124208/CLKIN
157880/CLKIN
615
528
3702
2441
1882
1579
233
262
2103
1627
1242
1187
μs
3
Delay from HRESET deassertion to SRESET deassertion
REFCLK = 33 MHz to 133 MHz
16/CLKIN
640
120
ns
Note:
Timings are not tested, but are guaranteed by design.
Figure 7. Timing for a Reset Configuration Write
Table 19. Timing for a Reset Configuration Write (continued)
No.
Characteristics
Expression
Max
Min
Unit
PORESET
HRESET
Input
Output (I/O)
SRESET
Output (I/O)
RCW_SRC2,RCW_SRC1,RCW_SRC0,STOP_BS and RCFG_CLKIN_RNG
pins must be valid
1
2
3
Reset configuration write
sequence during this
period.
相關(guān)PDF資料
PDF描述
MSC8144EVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144ESVT800B 133 MHz, OTHER DSP, PBGA783
MSC8144ESVT1000B 133 MHz, OTHER DSP, PBGA783
MSC8144EVT800B 133 MHz, OTHER DSP, PBGA783
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