參數(shù)資料
型號: MSC8144ETVT800B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 52/80頁
文件大小: 1251K
代理商: MSC8144ETVT800B
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 14
Freescale Semiconductor
56
Figure 26 provides the AC test load.
Figure 27 shows the MII receive AC timing diagram.
2.6.10.4
RMII Transmit and Receive AC Timing Specifications
Table 43 provides the RMII transmit and receive AC timing specifications.
Figure 26. AC Test Load
Figure 27. MII Receive AC Timing
Table 43. RMII Transmit and Receive AC Timing Specifications
Parameter/Condition
Symbol 1
Min
Max
Unit
REF_CLK duty cycle
tRMXH/tRMX
35
65
%
REF_CLK to RMII data TXD[1–0], TX_EN delay
tRMTKHDX
210
ns
RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK
tRMRDVKH
4.0
ns
RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK
tRMRDXKH
2.0
ns
REF_CLK data clock rise
tRMXR
1.0
4.0
ns
REF_CLK data clock fall
tRMXF
1.0
4.0
ns
Typical REF_CLK clock period (tRMX) is 20 ns
Notes:
1.
Typical REF_CLK clock period (tRMX) is 20 ns
2.
Program GCR4 as 0x00001405
Output
Z0 = 50 Ω
VDDGE/2
RL = 50 Ω
RX_CLK
RXD[3:0]
tMRDXKH
RX_DV
RX_ER
tMRDVKH
Valid Data
相關(guān)PDF資料
PDF描述
MSC8144EVT1000A 133 MHz, OTHER DSP, PBGA783
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MSC8144ESVT1000B 133 MHz, OTHER DSP, PBGA783
MSC8144EVT800B 133 MHz, OTHER DSP, PBGA783
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