參數(shù)資料
型號(hào): MSC8144SVT1000B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁(yè)數(shù): 48/80頁(yè)
文件大小: 1250K
代理商: MSC8144SVT1000B
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freescale Semiconductor
52
2.6.7
TDM Timing
Figure 18 shows the TDM input AC timing.
Note:
For some TDM modes, receive data and receive sync are input on other pins. This timing is also valid for them. See
the MSC8144 Reference Manual.
Figure 19 shows TDMxTSYN AC timing in TSO=0 mode.
Figure 20 shows the TDM Output AC timing
Table 37. TDM Timing
Characteristic
Symbol
Expression
Min
Max
Units
TDMxRCLK/TDMxTCLK
tTDMC
TC1
16
ns
TDMxRCLK/TDMxTCLK high pulse width
tTDMCH
(0.5
± 0.1) × TC4
7—
ns
TDMxRCLK/TDMxTCLK low pulse width
tTDMCL
(0.5
± 0.1) × TC4
7—
ns
TDM receive all input setup time related to TDMxRCLK
TDMxTSYN input setup time related to TDMxTCLK in TSO=0 mode
tTDMVKH
3.6
ns
TDM receive all input hold time related to TDMxRCLK
TDMxTSYN input hold time related to TDMxTCLK in TSO=0 mode
tTDMXKH
1.9
ns
TDMxTCLK high to TDMxTDAT output active2
tTDMDHOX
2.5
ns
TDMxTCLK high to TDMxTDAT output valid2
tTDMDHOV
—9.8
ns
All output hold time (except TDMxTSYN) 3
tTDMHOX
2.5
ns
TDMxTCLK high to TDMxTDAT output high impedance2
tTDMDHOZ
—9.8
ns
TDMxTCLK high to TDMxTSYN output valid2
tTDMSHOV
—9.25
ns
TDMxTSYN output hold time3
tTDMSHOX
2.0
ns
Notes:
1.
Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.
2.
Values are based on 20 pF capacitive load.
3.
Values are based on 10 pF capacitive load.
4.
The expression is for common calculations only.
Figure 18. TDM Inputs Signals
Figure 19. TDMxTSYN in TSO=0 mode
TDMxRCLK
TDMxRDAT
TDMxRSYN
tTDMC
tTDMCH
tTDMCL
tTDMVKH
tTDMXKH
TDMxTCLK
TDMxTSYN
tTDMVKH
tTDMXKH
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