參數(shù)資料
型號： MSC8144SVT1000B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù)： 77/80頁
文件大?。?/td> 1250K
代理商： MSC8144SVT1000B
Revision History
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
79
7
Dec 2007
Changed minimum voltage level for VDDM3 to 1.213 (1.25 – 3%) in Table 3.
Added POS to titles in Section 2.6.6.
Added additional signals to titles in Section 2.6.8. Added high and low voltage ranges to Table 19.
Added ATM and POS to headings in Section 2.7.11. Changed characteristics to generic input/output in Table 52,
Figure 33, and Figure 34.
Replaced Sections 2.7.13 and 2.7.14 with new Section 2.7.13, Asynchronous Signal Timing. Renumbered
subsequent sections, tables, and figures.
Added POS to all UTOPIA references in Section 3.4.5.
8
Dec 2007
Changed GCR4 program value to 0x0004C130 in Note 7 in Table 51.
9
Mar 2008
Changed description of Table 20 in Section 2.7.2.
10
Apr 2008
Added 3 to the PLL supply voltage row in Table 2.
Changed the first sentence in Section 3.4.8 to reflect that Table 70 indicates what to do with pins if they are
“not” required by the design. Changed the Pin Connection for GPIO[0–31] to GND.
Updated ordering information in Section 4.
Multiple corrections of minor punctuation errors.
11
Aug 2008
Removed the comment about preliminary estimates before Table 4 and removed non-DDR rows in the table.
Table 9 and Table 11 for DDR and DDR2 SDRAM capacitance removed and subsequent tables renumbered.
Changed units for IOH and IOL to mA in Table 9.
Removed signal low and high input current from Table 12.
Added a note to Table 15 to exclude TDM and TMS. Removed reference to overshoot and undershoot and
associated figure.
Changed minimum clock frequency to 33 MHz and maximum clock frequency to 133 MHz in Table 16.
Deleted old Table 17 Clock Parameters.
Changed minimum input clock frequency to 33 MHz in Table 19.
Changed the tDDKHAX minimum value in Table 23 to 1.85 ns.
Removed tREFPJ and tREFCJ from Table 24 because the specifications are not required or tested.
Removed tPCRSTCLK, tPCRSTOFF, tPCRST, and tPCRHFA from Table 36 because the specifications are not required
or tested.
Removed tUAVKH and tUAVXH from Table 38 because the specifications are not required or tested.
The parameters tMDCH, tMDCR, and tMDHF were removed from Table 40 because the specifications are not
required or tested.
The parameters tMTXH/tMTX, tMTXR, and tMTXF were removed from Table 41 because the specifications are not
required or tested.
The parameters tMRXH/tMRX, tMRXR, and tMRXF were removed from Table 42 because the specifications are not
required or tested.
The parameters tRMXH/tRMX, tRMXR, and tRMXF were removed from Table 43 because the specifications are not
required or tested.
Removed the parameters tRGT, tRGTH/tRGT (1000Base-T), tRGTH/tRGT (10Base-T), tRGTR, tRGTF, tG12, and
tG125H/tG125 were removed from Table 45 and Table 46 because the specifications are not required or tested.
Changed tUEKHOX to guaranteed by design in Table 47.
Updated Figure 35 and Figure 36 SPI timing diagrams.
Removed TCK rise and fall time from Table 50.
Updated orderable part numbers in Section 4.
12
Aug 2008
Changed b8t to bit in the M3 memory description on the first page.
Changed maximum input high voltage (VIH) for SPI to 3.465 in the first row of Table 14.
Changed packet processor to QUICC Engine Subsystem in the last row of Table 18.
13
Feb 2009
In Figure 31, for GTX_CLK, changed (at transmitter) to (at DSP) and for RX_CLK, changed (at PHY) to (at
DSP).
Updated package drawing to the latest revision, Case No. 1842-04 in Figure 44.
14
Jul 2009
Updated MVREF equations and temperature ranges in Table 3.
Updated orderable part numbers to Section 4.
15
Nov 2009
Updated Core and PLL input voltage tolerance in Table 3.
16
May 2010
Corrected typo in Table 23. Changed MCLK minimum time to 5 ns.
Table 66. Document Revision History (continued)
Rev.
Date
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC8144SVT800A 功能描述:IC DSP QUAD 800MHZ 783FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8144SVT800B 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144TVT1000A 功能描述:IC DSP QUAD 1GHZ 783FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
MSC8144TVT1000B 制造商:Freescale Semiconductor 功能描述:PACSUN REV2.1 NON-E - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144TVT800A 功能描述:IC DSP QUAD 800MHZ 783FCBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
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