參數(shù)資料
型號(hào): MSC8144VT1000A
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 50/80頁(yè)
文件大?。?/td> 0K
描述: IC DSP QUAD 1GHZ 783FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: StarCore
類(lèi)型: SC3400 內(nèi)核
接口: 以太網(wǎng),I²C,SPI,TDM,UART,UTOPIA
時(shí)鐘速率: 1.0GHz
非易失內(nèi)存: 外部
芯片上RAM: 10.5MB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.00V
工作溫度: 0°C ~ 90°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 783-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤(pán)
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
54
2.6.9
Timer Timing
Figure 23 shows the timer input AC timing
2.6.10
Ethernet Timing
This section describes the AC electrical characteristics for the Ethernet interface.
There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is
a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144 Reference
Manual.
2.6.10.1
Management Interface Timing
Table 39. Timer Timing
Characteristics
Symbol
Min
Unit
TIMERx frequency
TTMREFCLK
10.0
ns
TIMERx Input high phase
TTMCH
4.0
ns
TIMERx Output low phase
TTMCL
4.0
ns
Figure 23. Timer Timing
Table 40. Ethernet Controller Management Interface Timing
Characteristics
Symbol
Min
Max
Unit
ETHMDC to ETHMDIO delay2
tMDKHDX
10
70
ns
ETHMDIO to ETHMDC rising edge setup time
tMDDVKH
7—
ns
ETHMDC rising edge to ETHMDIO hold time
tMDDXKH
0—
ns
Notes:
1.
Program the ETHMDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the
source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz, to
achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8144 Reference Manual for
configuration details.
2.
The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of
333 MHz, the delay is 58 ns.
TTMREFCLK
TTMCL
TTMCH
TIMERx (Input)
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