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參數(shù)資料
| 型號： | MSC8144VT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 133 MHz, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783 |
| 文件頁數(shù)： | 30/80頁 |
| 文件大小： | 1250K |
| 代理商： | MSC8144VT800B |
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MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Electrical Characteristics
Freescale Semiconductor
36
2.6.3
Reset Timing
The MSC8144 has several inputs to the reset logic:
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
JTAG reset
RapidIO reset
Software hard reset
Software soft reset
All MSC8144 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset.
The reset status register indicates the most recent sources to cause a reset. Table 17 describes the reset sources.
Table 17. Reset Sources
Table 18 summarizes the reset actions that occur as a result of the different reset sources.
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC8144 and configures various attributes of the
MSC8144. On PORESET, the entire MSC8144 device is reset. All PLLs states is reset, HRESET
and SRESET are driven, the extended cores are reset, and system configuration is sampled. The
reset source and word are configured only when PORESET is asserted.
External hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC8144. While HRESET is
asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and
SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that
the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on
reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144
Reference Manual.
External soft reset
(SRESET)
Input/ Output
Initiates the soft reset flow. The MSC8144 detects an external assertion of SRESET only if it occurs
while the MSC8144 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is
driven, the extended cores are reset, and system configuration is maintained.
Host reset
command through
the TAP
Internal
When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the
soft reset signal and an internal soft reset sequence is generated.
Software
watchdog reset
Internal
When the MSC8144 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
RapidIO reset
Internal
When the RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset
sequence.
Software hard
reset
Internal
A hard reset sequence can be initialized by writing to a memory mapped register (RCR)
Software soft reset
Internal
A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
Table 18. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
External only
External or Internal
(Software Watchdog,
Software or RapidIO)
External or
internal
Software
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.6.3.2 for details).
Yes
NoNoNo
PLL state reset
Yes
No
Select reset configuration source
Yes
No
System reset configuration write
Yes
No
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| MSC8151SVT1000B | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Darwin RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MSC8151TVT1000B | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Darwin RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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