參數(shù)資料
型號(hào): MSM5117400D
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 4,194,304-Word 】 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
中文描述: 4194304詞】4位動(dòng)態(tài)隨機(jī)存儲(chǔ)器:快速頁(yè)面模式型
文件頁(yè)數(shù): 8/14頁(yè)
文件大小: 160K
代理商: MSM5117400D
MSM5117400D
8/14
Notes:
1.
A start-up delay of 200
μ
s is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2.
The AC characteristics assume t
T
= 5ns.
3.
V
IH
(Min.) and V
IL
(Max.) are reference levels for measuring input timing signals. Transition times
(t
T
) are measured between V
IH
and V
IL
.
4.
This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5.
Operation within the t
RCD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RCD
(Max.) is specified as a reference point only. If t
RCD
is greater than the specified t
RCD
(Max.)
limit, then the access time is controlled by t
CAC
.
6.
Operation within the t
RAD
(Max.) limit ensures that t
RAC
(Max.) can be met.
t
RAD
(Max.) is specified as a reference point only. If t
RAD
is greater than the specified t
RAD
(Max.)
limit, then the access time is controlled by t
AA
.
7.
t
OFF
(Max.) and t
OEZ
(Max.) define the time at which the output achieved the open circuit condition
and are not referenced to output voltage levels.
8.
t
RCH
or t
RRH
must be satisfied for a read cycle.
9.
t
WCS
, t
CWD
, t
RWD
, t
AWD
and t
CPWD
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If t
WCS
t
WCS
(Min.), then the cycle is an early write
cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t
CWD
t
CWD
(Min.), t
RWD
t
RWD
(Min.), t
AWD
t
AWD
(Min.) and t
CPWD
t
CPWD
(Min.), then the cycle is a
read modify write cycle and data out will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is
latched and remains in effect until the exit cycle is generated. In a test mode CA0 and CA1 are not
used and each DQ pin now accesses 4-bit locations. Since all 4DQ pins are used, a total of 16 data
bits can be written in parallel into the memory array. In a read cycle, if 4 data bits are equal, the DQ
pin will indicate a high level. If the 4 data bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating state by
performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified
value. These parameters should be specified in test mode cycle by adding the above value to the
specified value in this data sheet.
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