- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378005 > MSM514212 (OKI SEMICONDUCTOR CO., LTD.) 5,048-Word x 8-Bit Line Memory PDF資料下載
參數(shù)資料
| 型號： | MSM514212 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 5,048-Word x 8-Bit Line Memory |
| 中文描述： | 5,048字× 8位線存儲器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 1398K |
| 代理商： | MSM514212 |
8/15
Semiconductor
MSM514212
OPERATION MODE
Write Cycle
When
WE
input is enabled (at the "L" level), the write cycle is executed by synchronizing it with
the WCK clock input. Read and write data is processed by the same clock in the write cycle to
carry out the video processing. Data is input after a delay of oneline (5048 bits) is input at the
rising edge of the clock in the write cycle.
In addition, when the length of the delay is controlled by
WE
, the value of the delay bits is from
40 to 5048. The
WR
operation must be performed now to write the last data to memory cell.
Read Cycle
When
RE
input is enabled (at the "L" level), the read cycle is executed by synchronizing it with
the RCK clock input. Data is output at t
AC
(or t
ACR
). In addition, when the length of the delay
is controlled by
RE
, the value of the delay bits is from 40 to 5048.
Write Reset Cycle
Read Reset Cycle
When the power supply is on, the address values of the read and write address pointers are at
random. Thus, each pointer must be initialized by the
RR
signal and the
WR
signal beforehand.
Data can be input (to address 0) with the first cycle after this reset operation.
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100
m
s after V
CC
has
stabilized to a value within the range of recommended operating conditions. After this 100
m
s
stabilization interval, the following initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 18
dummy write operations (WCK cycles) and read operations (RCK cycles) must be performed,
followed by a
WR
operation and an
RR
operation, to properly initialize the write and the read
address pointer. Dummy write cycles/
WR
and dummy read cycles/
RR
may occur simultaneously.
If these dummy read and write operations start while V
CC
and/or the substrate voltage has not
stabilized, it is necessary to perform an
RR
operation plus a minimum of 18 RCK cycles plus
another
RR
operation, and a
WR
operation plus a minimum of 18 WCK cycles plus another
WR
operation to properly initialize read and write address pointers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM514221B-30JS | 262,263-Word x 4-Bit Field Memory |
| MSM514221B-30RS | 262,263-Word x 4-Bit Field Memory |
| MSM514221B-30ZS | 262,263-Word x 4-Bit Field Memory |
| MSM514221B-40JS | 262,263-Word x 4-Bit Field Memory |
| MSM514221B-40RS | 262,263-Word x 4-Bit Field Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM514221B | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,263-Word x 4-Bit Field Memory |
| MSM514221B-30 | 制造商:OK International 功能描述: |
| MSM514221B-30JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,263-Word x 4-Bit Field Memory |
| MSM514221B-30RS | 制造商:OK International 功能描述:FIELD/FRAME/LINE MEMORY, 16 Pin, Plastic, DIP |
| MSM514221B-30ZS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:262,263-Word x 4-Bit Field Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。