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參數(shù)資料
| 型號： | MSM58321RS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 121K |
| 代理商： | MSM58321RS |
Semiconductor
MSM58321
20
Figure 12
BUSY
1 Hz (inside IC)
WRITE input
1 sec
If a count operation is continued by setting the STOP input to the L level, write operation must be performed, in
principle, while the BUSY output is at the H level. While the BUSY output is at the L level, count operations are
performed by the digit counters and write operation is inhibited, but there is a marginal period of 244 s from the
BUSY output trailing edge. If the BUSY output goes to the L level during a write operation, the write operation is
stopped temporarily within 244 s and it is restarted when the BUSY output goes to the H level again. Figure 12
shows a time chart of BUSY output, 1 Hz signal inside the IC, and WRITE input.
Figure 13
32,768 kHz
OSC
15-stage
frequency
divider
circuit
Stages
11~15
1~10 stage
015
R
BUSY
R
1 Hz
BUSY
STOP
WRITE
N
RESET
STOP
WRITE
Rp
CS
From ADDRESS DECODER
A0 A1 A2 A3
H
L
H
t3
t1
t2
O15
(inside IC)
1 Hz
(inside IC)
RESET (inside IC)
t1 = 1000.1221 ±31.25 ms
t2 = 1000.3663 ±31.25 ms
t3 = 1000 ±31.25 ms
Rp
D
Frequency divider and
BUSY circuit reset
If A0 ~ A3 = HLHH is input to ADDRESS DECODER, the DECODER output (D) goes to the H level. If CS1 = CS2 =
H and WRITE = H in this state, the 5 poststage in the 15-stage frequency divider and the BUSY circuit are reset.
In this period, the BUSY output remains at the H level and the 1 Hz signal inside the IC remains at the L level, and
counting is stopped. If this reset is inactivated while the oscillator operates, the BUSY output goes to the L level after
1000.1221 ±31.25 ms and the 1 Hz signal inside the IC goes to the H level after 1000.3663 ±31.25 ms. These times
are not the same because the first ten stages in the 15-stage frequency divider are not reset. (See Figure 13)
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