參數(shù)資料
型號: MSM62X42BRS
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDIP18
封裝: 0.300 INCH, PLASTIC, DIP-18
文件頁數(shù): 11/28頁
文件大?。?/td> 219K
代理商: MSM62X42BRS
Semiconductor
MSM62X42B
58
Reading and Writing of Registers S1 ~ W and Writing of 30-Second ADJ Bit
Registers S1 ~ W (Addresses 0 ~ C)
YES
NO
HOLD bit
¨ 1
BUSY bit = 0 ?
Write data into or
Read data from
registers S1~W
READ BUSY bit
HOLD bit
¨ 0
Reading and writing in the case of using HOLD bit
Idling time
HOLD bit
¨ 0
In the inside of LSI, the CLEAR of BUSY bit is performed when
HOLD bit = 0, but, if the period of HOLD bit =0 is extermely
narrow as compared with the period of HOLD bit = 1, there is
some case that the CLEAR of BUSY bit delays so that the
BUSY bit can be cleared by sampling HOLD bit = 0 at approximate
16KHz. It is recommended to allow an idling time of 62
ms or more.
*
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