Semiconductor
MSM62X42B
56
The low-level pulse width of the fixed cycle waveform is 7.8125ms independent of t0/t1
inputs.
The fixed cycle output waveform mode is available for the confirmation of the crystal
oscilltor frequency.
During
±30 second adjustment a carry can occur that will cause the STD.P output to go
"L" when t0/t1=1,0 or 1,1. However, when ITRPT/STND bit=0, the "L" is kept from
clearing under the second of 30-second ADJ to resuming a carry to 1/64-second digit.
No STD.P output change occurs as a result of writing data to registers S1 ~ H1.
CF REGISTER (control F Register)
a) REST (D0) (RESET)
This bit is used to reset the clock's internal counter of less than a second. When RTEST=1, the
counter is Reset for the duration of REST. In order to release this counter from Reset, a "0"
must be written to the REST bit. If CS1=0, then REST=0 automatically.
b) STOP (D1) (STOP)
This bit is used for the integrating clock. When "1" is written, the timing after 8,192Hz stops
and swhen "0" is written, the timing starts again.
c) 24/12 (D2) (24 Hour/12 Hour)
This bit is for selection of 24/12 hour time modes, if D2=1, 24 hour mode is selected and
the PM/AM bit is invalid. If D2=0,12 hour mode is selected and the PM/AM bit is valid.
The writing into the 24/12 hour bit is performed only when RESET bit=1. [24/12 hour
bit=*1 and RESET bit="1"] must be written and then [24/12 hour bit=*2 and RESET
bit="0"] must be written continuously. However, in the case of *1=*2 and *1
≠*2, the 24/
12 hour bit becomes indefinite.
When 24/12 hour bit is rewritten, the data of more than H1 may be destroyed. Therefore,
the data of more than H1 must be newly rewritten.
When REST bit=0, the 24/12 hour bit cannot be written.
d) TEST (D3)
This is a bit for the test. This bit is used in the state of TEST bit=0.
When TEST bit is "1", because of the test function based on our company's convenience,
the user's function is not guaranteed.
"1"
"0"
"1"
STOP BIT
TIMING OF
"CARRY"
TO 8192Hz
"CARRY" EXECUTED
"CARRY" NOT EXECUTED
"1"