參數(shù)資料
型號(hào)： MSM63182-XXX
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 2 MHz, MICROCONTROLLER, UUC107
封裝： 4.44 X 4.92 MM, 0.35 MM HEIGHT, DIE-107
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 241K
代理商： MSM63182-XXX
Semiconductor
MSM63182
16/27
ELECTRICAL CHARACTERISTICS
DC Characteristics
Parameter
Symbol
Condition
Mea-
suring
Circuit
Unit
1.9
1.8
1.7
VDD2 Voltage
Max.
Typ.
Min.
VDD2
1/5 bias, 1/4 bias
(Ta = 25°C)
V
—
–4
—
VDD2 Voltage Temperature Deviation
DVDD2
—
mV/°C
Typ.+ 0.3
3/2
VDD2
Typ.– 0.3
VDD3 Voltage
VDD3
1/5 bias
V
Typ.+ 0.4
2
VDD2
Typ.– 0.4
VDD4 Voltage
VDD4
1/5 bias
V
Typ.+ 0.5
5/2
VDD2
Typ.– 0.5
VDD5 Voltage
VDD5
1/5 bias
V
—
1.0
Crystal Oscillation Start Voltage
VSTA
Oscillation start time:
within 5 seconds
V
—
0.9
Crystal Oscillation Hold Voltage
VHOLD
Backup
V
5.0
—
0.1
Crystal Oscillation Stop Detect Time
TSTOP
—ms
25
—
5
External Crystal Oscillator Capacitance
CG
—pF
30
25
20
Internal Crystal Oscillator Capacitance
CD
—pF
16
12
8
Internal RC Oscillator Capacitance
COS
—pF
—
30
—
External Ceramic Oscillator
Capacitance
CL0, 1
CSA2.00MG (Murata
MFG.-make) used
VDD = 3.0 V
pF
0.4
—
0.0
POR Voltage
VPOR1
VDD = 1.5 V
V
1
0.7
—
0.0
VDD = 3.0 V
V
—
1.7
Backup not used
V
2.0
1.5
1.0
VDDL Voltage
VDDL
High-speed clock
oscillation stopped
V
5.5
—
1.2
High-speed clock oscillation
(VDD = 1.2 to 5.5 V)
V
VDDH
2.7
—
2.0
VDDH Voltage
(Backup used)
High-speed clock oscillation
(Ceramic oscillation, 1 MHz)
VDD = 1.5 V
V
High-speed clock oscillation
stopped
VDD = 1.5 V
3.0
—
2.8
V
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = –20 to +70°C unless otherwise specified)
Typ.+ 0.2
1/2
VDD2
Typ.– 0.2
VDD1 Voltage
VDD1
1/5 bias, 1/4 bias
V
Typ.+ 0.2
VDD2
Typ.– 0.2
1/4 bias (connect
VDD3 and VDD2)
Typ.+ 0.3
3/2
VDD2
Typ.– 0.3
1/4 bias
Typ.+ 0.4
2
VDD2
Typ.– 0.4
1/4 bias
1.5
—
1.2
Non-POR Voltage
VPOR2
VDD = 1.5 V
V
3.0
—
2.0
VDD = 3.0 V
V
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system
reset occurs.
2. "POR" denotes Power On Reset.
3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises
up to VDD.
4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and
again rises up to VDD.
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