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參數(shù)資料
| 型號(hào)： | MSM6542-02RS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP18 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-18 |
| 文件頁(yè)數(shù)： | 10/54頁(yè) |
| 文件大?。?/td> | 406K |
| 代理商： | MSM6542-02RS |
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Semiconductor
MSM6542-01/02/03
85
i)
In the periodic interrupt mode (when the IT/PLS
1, bit is 1)
*1
When DP = 1, the open state is not entered until a certain period
passes after an interrupt is generated. (See the description of the C
E
register.)
*2
However, when DP = 1, if the IRQ FLAG
1 bit is read out within
122
s after an interrupt is generated, it is cleared after 122s from the
generation of the interrupt.
ii)
In the periodic pulse output mode (when the IT/PLS
1 bit is 0.)
The open status is entered when the IRQ FLAG1
is read. (*1)
No interrupt occurs
because the MASK1 bit is 1.
Open
Low level
Interrupt timing
"0"
"1"
INTERRUPT OUT (-01, -02)
PERIODIC OUT (-03)
MASK1 bit
When the IRQ FLAG1 is read during masking,
IRQ FLAG1 is not cleared. (*2)
When 0 is written in the IRQ FLAG1 bit,
the open state is entered without having
to wait for automatic restration
The low level is not output
because the MASK1 bit is 1.
Open
Low level
Output timing
"0"
"1"
MASK1 bit
Automatic restoration
INTERRUPT OUT
(-01, -02)
PERIODIC OUT
(-03)
"1"
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