參數(shù)資料
型號(hào)： MSM6542-3GS-VK
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類(lèi)： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO24
封裝： 0.430 INCH, PLASTIC, SOP-24
文件頁(yè)數(shù)： 20/55頁(yè)
文件大?。?/td> 361K
代理商： MSM6542-3GS-VK
Semiconductor
MSM6542-01/02/03
93
ae8
Alarm comparlson range
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
None
A ~ S1
A-S1 ~ A-S10
A-S1 ~ A-MI1
A-S1 ~ A-MI10
A-S1 ~ A-H1
A-S1 ~ A-H10
A-S1 ~ A-D1
A-S1 ~ A-D10
A-S1 ~ A-MO1
A-S1 ~ A-MO10
A-S1 ~ A-H10, A-W
A-S1 ~ A-D1, A-W
A-S1 ~ A-D10, A-W
A-S1 ~ A-MO1, A-W
A-S1 ~ A-MO10, A-W
ae4
ae2
ae1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C
C’ Register (Control C' Register)
This register is a test register. The user can use it when both the TEST
1 (D0) and TEST2 (D1) bits
of the register are 0. When either or both TEST bits are 1, Oki's test functions are enabled, making
the execution results of user's functions unpredictable.
When the register is read, it is automatically cleared. The read value is always 0. When 1 is
written in the REST (D
2) bit of the CE register, the CC' register is automatically set at 0.
C
D’ Register (Control D' Register)
This register sets an interrupt period when the IT/PLS
1 (D2) bit of the CD register is 1 and a pulse
output period when the bit is 0. The following table shows the relationships between the status
of the C
D' register bits and the length of periods.
相關(guān)PDF資料
PDF描述
MSM6542-3RS 1 TIMER(S), REAL TIME CLOCK, PDIP24
MSM6542-2RS 1 TIMER(S), REAL TIME CLOCK, PDIP18
MSM6542-3GS-VK 1 TIMER(S), REAL TIME CLOCK, PDSO24
MSM6542-2MSK 1 TIMER(S), REAL TIME CLOCK, PDSO20
MSM6546-XXGS-K 4-BIT, MROM, MICROCONTROLLER, PQFP100
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