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參數(shù)資料
| 型號： | MSM65X227TS-K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, EEPROM, 6 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 142K |
| 代理商： | MSM65X227TS-K |
10/18
MSM65X227
Semiconductor
AC Characteristics
External memory control
(VDD=AVDD=VRH=4.5 to 5.5V, GND=AGND=VRL=0V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
Clock Cycle
tC
167
—
"L" Clock Pulse Width
tCLW
75
—
"H" Clock Pulse Width
tCHW
CL=100pF
75
—
ALE Pulse Width
tAW
tC+tCHW–40
—
ALE Pulse Delay Time 1
tALD1
tCLW–20
—
ALE Pulse Delay Time 2
tALD2
tCLW–20
—
RD Pulse Width
tRW
tC+tCHW–40
—
RD Pulse Delay Time
tRD
tCLW–20
tCLW+40
WR Pulse Width
tWW
tC+tCHW–40
—
WR Pulse Delay Time
tWD
tCLW–20
tCLW+40
"L" Address Setup Time
tLAS
tC–40
—
"H" Address Setup Time
tHAS
tC+tCHW–40
—
"L" Address Hold Time
tLAH
tCLW–20
—
Bus Floating Time
tLAZ
—20
"H" Address Hold Time
tHAHR
tCLW–20
—
"H" Address Hold Time
tHAHW
tCLW–20
—
Read Data Access Time
tRDAA
—tC+tCLW–15
Read Data Access Time
tRDAR
—tCHW+10
Read Data Hold Time
tRDH
0—
Write Data Hold Time
tWDS
tC+tCHW–40
—
Write Data Hold Time
tWDH
tCLW–20
—
ns
CPU control
(VDD=AVDD=4.5 to 5.5V, GND=AGND=0V, Ta=–40 to +85°C)
Parameter
Symbol
Condition
Min.
Max.
Unit
RESET Pulse Width *1
tRESW1
20
—
ns
RESET Pulse Width *2
tRESW2
oscillation
stabilization
time
—
*1 Except during power-on, sleep, and hardware stop modes
*2 During power-on, sleep, and hardware stop modes
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