3-6
MSM66577 Family User's Manual
Chapter 3 CPU Control Functions
3.2.3 Examples of Standby Function Register Settings
HALT mode setting
(1)
Standby control register (SBYCON)
Setting bit 1 (HLT) to "1" changes the mode to the HALT mode.
HOLD mode setting
(1)
Port 9 mode register (P9IO)
If HLDACK (HOLD mode transfer output pin) is to be used, set bit 7 (P9IO7) to "1" to
configure that port as an output.
(2)
Port 9 secondary function control register (P9SF)
If HLDACK (HOLD mode transfer output pin) is to be used, set bit 7 (P9SF7) to "1" to
configure that port as a secondary function output.
(3)
Peripheral control register (PRPHCON)
Set bit 5 (HOLD) to "1" to enable the HOLD pin input. The mode changes to the HOLD mode
when an external device inputs a high level to the HOLD pin. After the transfer to the HOLD
mode is complete, the HLDACK output is set to "1" as an acknowledge signal.
STOP mode setting
(1)
Stop code acceptor (STPACP)
Write n5H, nAH (n = 0 to F) consecutively.
(2)
Standby control register (SBYCON)
If output ports are to be high impedance during the STOP mode, set bit 2 (FLT) to "1". If
oscillation of the main clock (OSCCLK) is not to be terminated during the STOP mode, reset
bit 3 (OSCS) to "0". To terminate oscillation of the main clock (OSCCLK), set bit 3 (OSCS)
to "1" and specify with bits 4 and 5 (OST0 and OST1) the oscillation stabilization time after
the main clock resumes. Setting bit 0 (STP) to "1" changes the mode to the STOP mode.
3.2.4 Operation of Each Standby Mode
(1)
HALT mode
Setting bit 1 (HLT) of the standby control register (SBYCON) to "1" changes the mode to
the HALT mode.
In the HALT mode, the clock (CPUCLK) supply to the CPU is terminated, but the clock
(CPUCLK) is supplied to internal peripheral modules (TBC, WDT, general-purpose 8/16-
bit timers, serial ports, etc.) so their operation continues. Because the CPU is halted,
instructions are not executed. Instruction execution stops at the beginning of the next
instruction (following the instruction that set bit 1 (HLT) of SBYCON to "1").
HALT mode is released when any of the following occur: an interrupt request, reset by the
RES pin input, or reset by overflow of the watchdog timer.